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rt7231/32/33/34 ? ds7231/32/33/34-00 march 2013 www.richtek.com 1 copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? general description the rt7231/32/33/34 is a synchronous step-down dc/ dc converter with advanced constant on-time (acot tm ) mode control. it achieves high power density to deliver up to 4a output current from a 4.5v to 18v input supply. the proprietary acot tm mode offers an optimal transient response over a wide range of loads and all kinds of ceramic capacitors, which allows the device to adopt very low esr output capacitor for ensuring performance stabilization. in addition, rt7231/32/33/34 keeps an excellent constant switching frequency under line and load variation and the integrated synchronous power switches with the acot tm mode operation provides high efficiency in whole output current load range. cycle-by-cycle current limit provides an accurate protection by a valley detection of low side mosfet and external soft-start setting eliminates input current surge during startup. protection functions include thermal shutdown for rt7231/32/33/34, output under voltage protection (uvp) / over voltage protection (ovp) for rt7231/32. when the uvp/ovp is triggered, the device will enter latch mode for tssop-14 (exposed pad), and hiccup mode for wdfn-10l 3x3. the rt7231/32 are available in tssop-14 (exposed pad) and wdfn-10l 3x3 packages, and the rt7231 is operated in forced continuous conduction mode. the rt7233/34 are available in the sop-8 (exposed pad) package, and the rt7233 is operated in forced continuous conduction mode. features z z z z z acot tm mode enables fast transient response z z z z z 4.5v to 18v input voltage range z z z z z 4a output current z z z z z 50m internal low site n-mosfet z z z z z advanced constant on-time control z z z z z support all ceramic capacitors z z z z z up to 95% efficiency z z z z z 650khz switching frequency at all load current (rt7231, rt7233) z z z z z discontinuous operating mode at light load (RT7232, rt7234) z z z z z adjustable output voltage from 0.765v to 8v z z z z z adjustable soft-start z z z z z cycle-by-cycle current limit z z z z z input under voltage lockout z z z z z thermal shutdown z z z z z rohs compliant and halogen free applications z industrial and commercial low power systems z computer peripherals z lcd monitors and tvs z green electronics/appliances z point of load regulation for high-performance dsps, fpgas, and asics simplified application circuit 4a, 18v, 650khz, acot tm synchronous step-down converter * : vcc pin for tssop-14 (exposed pad) only. vs pin for tssop-14 (exposed pad) only. gnd pin for tssop-14 (exposed pad) only. pgood pin for tssop-14 (exposed pad) and wdfn-10l 3x3 only. pgood* rt7231/32/33/34 vreg5 fb vcc* v in boot sw ss v out vin gnd* pgnd en enable power good vs*
rt7231/32/33/34 2 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. rt7234 package type sp : sop-8 (exposed pad-option 2) lead plating system g : green (halogen free and pb free) RT7232 package type cp : tssop-14 (exposed pad) qw : wdfn-10l 3x3 (w-type) lead plating system g : green (halogen free and pb free) rt7233 package type sp : sop-8 (exposed pad-option 2) lead plating system g : green (halogen free and pb free) rt7231 package type cp : tssop-14 (exposed pad) qw : wdfn-10l 3x3 (w-type) lead plating system g : green (halogen free and pb free) ordering information discontinuous operating mode note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information pin configurations (top view) tssop-14 (exposed pad) 1q= : product code ymdnn : date code rt7231gqw rt7233gsp : product number ymdnn : date code rt7233gsp rt7231gcp : product number ymdnn : date code rt7231gcp sop-8 (exposed pad) wdfn-10l 3x3 en fb pgood ss vin vin boot sw sw vreg5 9 8 7 9 1 2 3 4 5 10 pgnd 11 en fb vreg5 ss vin boot pgnd sw pgnd 2 3 4 5 6 7 8 9 rt7234gsp : product number ymdnn : date code rt7234gsp 1p= : product code ymdnn : date code RT7232gqw RT7232gcp : product number ymdnn : date code RT7232gcp continuous switching mode fb vin pgnd gnd ss vreg5 pgood en pgnd sw sw boot vs vcc 4 2 3 5 7 6 11 13 12 10 8 9 14 pgnd 15 rt7231gcp ymdnn 1q=ym dnn 1p=ym dnn RT7232gcp ymdnn rt7234 gspymdnn rt7233 gspymdnn
rt7231/32/33/34 3 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. functional pin description pin no. tssop-14 (exposed pad) wdfn-10l 3x3 sop-8 (exposed pad) pin name pin function 1 -- -- vs output voltage sense input. 2 2 2 fb feedback voltage input. it is used to regulate the output of the converter to a set value via an external resistive voltage divider. the feedback threshold voltage is 0.765v typically. 3 3 3 vreg5 internal regulator output. connect a 1 f capacitor to gnd to stabilize output voltage. 4 4 4 ss soft-start time setting. con nect an external capacitor between this pin and gnd to set the soft- start time. 5 -- -- gnd analog ground. 6 5 -- pgood open drain power good indicator output. 7 1 1 en enable control input. a logic-high enables the converter; a logic-low forces the ic into shutdown mode reducing the supply current to less than 10 a. 8, 9, 15 (exposed pad) 11 (exposed pad) 5, 9 (exposed pad) pgnd power ground. the exposed pad must be soldered to a large pcb and connected to pgnd for maximum power dissipation. 10, 11 6, 7 6 sw switch node. connect this pin to an external l-c filter. 12 8 7 boot bootstrap supply for high side gate driver. connect a 0.1 f capacitor between the boot and sw pin. 13 9, 10 8 vin power input. the input voltage range is from 4.5v to 18v. must bypass with a suitably large ( 10 f x 2) ceramic capacitor. 14 -- -- vcc supply voltage input for internal linear regulator to the control circuitry.
rt7231/32/33/34 4 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. function block diagram * : vcc pin for tssop-14 (exposed pad) only. vs pin for tssop-14 (exposed pad) only. gnd pin for tssop-14 (exposed pad) only. pgood pin for tssop-14 (exposed pad) and wdfn-10l 3x3 only. operation the rt7231/32/33/34 is a synchronous step-down converter with advanced constant on-time control mode. using the acot tm control mode can reduce the output capacitance and provide fast transient response. it can minimize the component size without additional external compensation network. power good (for tssop-14 (exposed pad) and wdfn-10l 3x3 only) after soft-start is finished, the power good function will be activated. when the fb is activated, the pgood will become an open-drain output. if the fb is below, the pgood pin will be pulled low. internal regulator the regulator provides 5v power to supply the internal control circuit. connecting a 1 f ceramic capacitor for decoupling and stability is required. soft-start in order to prevent the converter output voltage from overshooting during the startup period, the soft-start function is necessary. the soft-start time is adjustable and can be set by an external capacitor. current protection the inductor current is monitored via the internal switches in cycle-by-cycle. once the output voltage drops under uv threshold, the device will enter latch mode for tssop- 14 (exposed pad), and hiccup mode for wdfn-10l 3x3. uvlo protection to protect the chip from operating at insufficient supply voltage, the uvlo is needed. when the input voltage of vcc is lower than the uvlo falling threshold voltage, the device will be latch-off. output discharge control (for tssop-14 (exposed pad) only) when en pin is low, the rt7231/32 will discharge the output with an internal 50 mosfet connected between v out to gnd pin. thermal shutdown when the junction temperature exceeds the otp threshold value, the ic will shut down the switching operation. once the junction temperature cools down and is lower than the otp lower threshold, the converter will automatically resume switching vcc* por & reg driver boot vreg5 control vbias on-time v in fb min. off-time ripple gen. v ref zc comparator ss sw pgnd en vreg5 oc + - - 2a v reg5 uv & ov sw fb vs* vin comparator + - fb 0.9 x v ref pgood* gnd*
rt7231/32/33/34 5 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. recommended operating conditions (note 3) z supply voltage, vin ----------------------------------------------------------------------------------------------- 4.5v to 18v z junction temperature range ------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply voltage, vin, vcc --------------------------------------------------------------------------------------- ? 0.3v to 20v z switch voltage, sw ----------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) < 10ns ---------------------------------------------------------------------------------------------------------------- ? 5v to 25v z boot to sw -------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z en ---------------------------------------------------------------------------------------------------------------------- ? 0.3v to 20v z other pins ------------------------------------------------------------------------------------------------------------ ? 0.3v to 6v z power dissipation, p d @ t a = 25 c tssop-14 (exposed pad) --------------------------------------------------------------------------------------- 2.50w wdfn-10l 3x3 ------------------------------------------------------------------------------------------------------ 1.67w sop-8 (exposed pad) -------------------------------------------------------------------------------------------- 2.041w z package thermal resistance (note 2) tssop-14 (exposed pad), ja --------------------------------------------------------------------------------- 40 c/w wdfn-10l 3x3, ja ------------------------------------------------------------------------------------------------ 60 c/w wdfn-10l 3x3, jc ------------------------------------------------------------------------------------------------ 7.5 c/w sop-8 (exposed pad), ja --------------------------------------------------------------------------------------- 49 c/w sop-8 (exposed pad), jc -------------------------------------------------------------------------------------- 15 c/w z junction temperature range ------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ---------------------------- -------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------- ? 65 c to 150 c (v in = 12v, t a = 25 c, unless otherwise specified) electrical characteristics parameter symbol test conditions min typ max unit supply current shutdown current i shdn v en = 0v -- 1 10 a quiescent current i q v en = 5v, v fb = 0.8v -- 1 1.3 ma logic threshold logic-high 2 -- 18 en input voltage logic-low -- -- 0.4 v v fb voltage and discharge resistance t a = 25 c 0.757 0.765 0.773 feedback threshold voltage v fb t a = ? 40 c to 85 c 0.755 -- 0.775 v feedback input current i fb v fb = 0.8v -- 0.01 0.1 a vout discharge resistance r dis v en = 0v, v s = 0.5v -- 50 100 v reg5 output v reg5 output voltage v reg5 6v v in 18v, 0 < i vreg5 < 5ma 4.8 5.1 5.4 v
rt7231/32/33/34 6 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit line regulation 6v v in 18v, i vreg5 = 5ma -- -- 20 mv load regulation 0 < i vreg5 < 5ma -- -- 100 mv output current i vreg5 v in = 6v, v reg5 = 4v -- 70 -- ma r ds(on) high-side r ds(on)_h (v boot ? v sw ) = 5.5v -- 120 -- switch on resistance low-side r ds(on)_l -- 50 -- m current limit current limit i lim 4.7 5.4 7.5 a thermal shutdown thermal shutdown threshold t sd shutdown temperature -- 150 -- thermal shutdown hysteresis t sd -- 20 -- c on-time timer control on-time t on v in = 12v, v out = 1.05v -- 135 -- ns minimum off-time t off(min) v fb = 0.7v -- 260 310 ns soft-start ss charge current v ss = 0v -- 6 -- a ss discharge current v ss = 0.5v 0.1 0.2 -- ma uvlo uvlo threshold wake up v reg5 3.6 3.85 4.1 hysteresis 0.16 0.35 0.47 v power good v fb rising 85 90 95 pgood threshold v fb falling -- 85 -- % pgood sink current pgood = 0.5v 2.5 5 -- ma output under voltage and over voltage protection ovp trip threshold ovp detect 115 120 125 % ovp prop delay -- 5 -- s uvp trip threshold 65 70 75 uvp hysteresis -- 10 -- % uvp prop delay -- 250 -- s uvp enable delay t uvpen relative to soft-start time -- t ss x 1.7 -- ms
rt7231/32/33/34 7 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. typical application circuit * : vcc pin for tssop-14 (exposed pad) only. vs pin for tssop-14 (exposed pad) only. gnd pin for tssop-14 (exposed pad) only. pgood pin for tssop-14 (exposed pad) and wdfn-10l 3x3 only. rt7231/32/33/34 fb vcc* v in 10f x 2 c1 0.1f c2 boot l1 1.4h 0.1f c6 22f x 2 c7 sw ss 3.9nf c5 1f c4 v out 1.05v/4a 22k r2 c3 vin vs* 8.25k r1 en gnd* pgnd r3 100k input signal pgood* vreg5 power good table 1. suggested component values (v in = 12v) v out (v) r1 (k ) r2 (k ) c3 (pf) l1 ( h) c7 ( f) 1 6.81 22.1 -- 1.4 22 to 68 1.05 8.25 22.1 -- 1.4 22 to 68 1.2 12.7 22.1 -- 1.4 22 to 68 1.8 30.1 22.1 5 to 22 2 22 to 68 2.5 49.9 22.1 5 to 22 2 22 to 68 3.3 73.2 22.1 5 to 22 2 22 to 68 5 124 22.1 5 to 22 3.3 22 to 68 7 180 22.1 5 to 22 3.3 22 to 68
rt7231/32/33/34 8 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. typical operating characteristics output voltage vs. output current 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 0 0.5 1 1.5 2 2.5 3 3.5 4 output current (a) output voltage (v) v in = 18v v in = 12v v in = 5v v out = 1.05v RT7232/34 output voltage vs. output current 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 0 0.5 1 1.5 2 2.5 3 3.5 4 output current (a) output voltage (v) v in = 18v v in = 12v v in = 5v v out = 1.05v rt7231/33 feedback threshold voltage vs. temperature 0.750 0.755 0.760 0.765 0.770 0.775 0.780 -50 -25 0 25 50 75 100 125 temperature (c) feedback threshold voltage (v ) v in = 12v, v out = 1.05v, i out = 0a output voltage v s. input voltage 1.040 1.042 1.044 1.046 1.048 1.050 1.052 1.054 1.056 1.058 1.060 4 6 8 1012141618 input voltage (v) output voltage (v) v in = 4.5v to 18v, v out = 1.05v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) v in = 5v v in = 12v v in = 18v v out = 1.05v rt7231/33 efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) v in = 5v v in = 12v v in = 18v v out = 1.05v RT7232/34
rt7231/32/33/34 9 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. switching frequency vs. temperature 600 610 620 630 640 650 660 670 680 690 700 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (khz) 1 switching frequency vs. input voltage 600 610 620 630 640 650 660 670 680 690 700 4 6 8 1012141618 input voltage (v) switching frequency (khz) 1 current limit vs. input voltage 4.0 4.5 5.0 5.5 6.0 6.5 7.0 4 6 8 101214161820 input voltage (v) current limit (a) current limit vs. temperature 4.0 4.5 5.0 5.5 6.0 6.5 7.0 -50 -25 0 25 50 75 100 125 temperature (c) current limit (a) v in = 12v, v out = 1.05v load transient response time (100 s/div) v in = 12v, v out = 1.05v, i out = 1a to 4a rt7231/32/33/34 v out (5mv/div) i out (2a/div) load transient response time (100 s/div) v in = 12v, v out = 1.05v, i out = 0a to 4a v out (20mv/div) rt7231/33 i out (2a/div)
rt7231/32/33/34 10 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. power on from en time (500 s/div) v in = 12v, v out = 1.05v, i out = 4a i out (2a/div) v en (5v/div) v out (500mv/div) power off from en time (500 s/div) v in = 12v, v out = 1.05v, i out = 4a i out (2a/div) v en (5v/div) v out (500mv/div) power off from v in time (10ms/div) v in = 12v, v out = 1.05v, i out = 4a i out (5a/div) v in (5v/div) v out (1v/div) power on from v in time (2.5ms/div) v in = 12v, v out = 1.05v, i out = 4a i out (5a/div) v in (5v/div) v out (1v/div) switching time (1 s/div) v in = 12v, v out = 1.05v, i out = 1a i l (1a/div) v sw (10v/div) v out (5mv/div) switching time (1 s/div) v in = 12v, v out = 1.05v, i out = 4a i l (2a/div) v sw (10v/div) v out (5mv/div)
rt7231/32/33/34 11 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. uvlo voltage vs. temperature 3.4 3.5 3.6 3.7 3.8 3.9 4.0 -50 -25 0 25 50 75 100 125 temperature (c) uvlo voltage (v) falling rising power good from en turn off time (2.5ms/div) v in = 12v, v out = 1.05v, i out = 4a rt7231/32 i out (5a/div) v en (5v/div) v out (1v/div) v pgood (5v/div) power good from en turn on time (250 s/div) v in = 12v, v out = 1.05v, i out = 4a i out (5a/div) v en (5v/div) v out (1v/div) v pgood (5v/div) rt7231/32 en threshold voltage vs. temperature 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 -50 -25 0 25 50 75 100 125 temperature (c) en threshold voltage (v ) rising v in = 12v, v out = 1.05v falling
rt7231/32/33/34 12 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. application information the rt7231/32/33/34 is a synchronous high voltage buck converter that can support the input voltage range from 4.5v to 18v and the output current up to 2a. it adopts acot tm mode control to provide a very fast transient response with few external compensation components. pwm operation it is suitable for low external component count configuration with appropriate amount of equivalent series resistance (esr) capacitors at the output. the output ripple valley voltage is monitored at a feedback point voltage. the synchronous high side mosfet is turned on at the beginning of each cycle. after the internal on-time expires, the mosfet is turned off. the pulse width of this on-time is determined by the converter's input and output voltages to keep the frequency fairly constant over the entire input voltage range. advanced constant on-time control the rt7231/32/33/34 has a unique circuit which sets the on-time by monitoring the input voltage and sw signal. the circuit ensures the switching frequency operating at 700khz over input voltage range and loading range. soft-start the rt7231/32/33/34 contains an external soft-start clamp that gradually raises the output voltage. the soft-start timing can be programmed by the external capacitor between the ss and gnd pins. the chip provides a 2 a charge current for the external capacitor. if a 3.9nf capacitor is used, the soft-start will be 2.6ms (typ.). the available capacitance range is from 2.7nf to 220nf. ss ss c5 (nf) 1.365 t (ms) = i (a) chip enable operation the en pin is the chip enable input. pulling the en pin low (<0.4v) will shut down the device. during shutdown mode, the rt7231/32/33/34 's quiescent current drops to lower than 10 a. driving the en pin high (>1.6v, <18v) will turn on the device again. for external timing control, figure 3. resistor divider for lockout threshold setting to prevent enabling circuit when v in is smaller than the v out target value, a resistive voltage divider can be placed between the input voltage and ground and connected to the en pin to adjust ic lockout threshold, as shown in figure 3. for example, if an 8v output voltage is regulated from a 12v input voltage, the resistor r en2 can be selected to set input lockout threshold larger than 8v. figure 1. external timing control an external mosfet can be added to implement digital control on the en pin when no system voltage above 2v is available, as shown in figure 2. in this case, a 100k pull-up resistor, r en , is connected between the v in and en pins. mosfet q1 will be under logic control to pull down the en pin. figure 2. digital enable control circuit the en pin can also be externally pulled high by adding a r en resistor and c en capacitor from the vin pin (see figure 1). rt7231/32/33/34 en gnd v in r en c en en en gnd 100k v in r en q1 en rt7231/32/33/34 en gnd v in r en1 r en2 rt7231/32/33/34
rt7231/32/33/34 13 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. output voltage setting the resistive divider allows the fb pin to sense the output voltage as shown in figure 4. figure 4. output voltage setting out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve under voltage lockout protection the rt7231/32/33/34 has under voltage lockout protection (uvlo) that monitors the voltage of pvcc pin. when the v pvcc voltage is lower than uvlo threshold voltage, the rt7231/32/33/34 will be turned off in this state. this is non-latch protection. over temperature protection the rt7231/32/33/34 equips an over temperature protection (otp) circuitry to prevent overheating due to excessive power dissipation. the otp will shut down switching operation when junction temperature exceeds 150 c. once the junction temperature cools down by approximately 25 c the main converter will resume operation. to keep operating at maximum, the junction temperature should be prevented from rising above 150 c. inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and an output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. the output voltage is set by an external resistive divider according to the following equation. it is recommended to use 1% tolerance or better divider resistors. ) out r1 v = 0.765(1 r2 + input and output capacitors selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the high side mosfet. a low esr input capacitor with larger ripple current rating should be used for the maximum rms current. the rms current is given by : out in rms out(max) in out v v i = i 1 vv ? this formula has a maximum at v in = 2v out , where i rms = i out / 2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor, two 10 f and 0.1 f low esr ceramic capacitors are recommended. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. the output ripple, v out , is determined by : out l out 1 viesr 8fc ?? ?? + ?? ?? the output ripple will be highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may need to meet the esr and rms current handling requirements. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must highest efficiency operation. however, it requires a large inductor to achieve this goal. for the ripple current selection, the value of i l = 0.2(i max ) will be a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? gnd fb r1 r2 v out rt7231/32/33/34
rt7231/32/33/34 14 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. figure 5. external bootstrap diode pvcc capacitor selection decouple with a 1 f ceramic capacitor. x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. over current protection when the output shorts to ground, the inductor current decays very slowly during a single switching cycle. an over current detector is used to monitor inductor current to prevent current runaway. the over current detector monitors the voltage between sw and gnd during the low side mos turn-on state. this is cycle-by-cycle protection. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for tssop-14 (exposed pad) package, the thermal resistance, ja , is 40 c/w on a standard jedec 51-7 four-layer thermal test board. for wdfn-10l 3x3 package, the thermal resistance, ja , is 60 c/w on a standard jedec 51-7 four-layer thermal test board. for sop-8 (exposed pad) package, the thermal resistance, ja , is 49 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (40 c/w) = 2.50w for tssop-14 (exposed pad) package p d(max) = (125 c ? 25 c) / (60 c/w) = 1.67w for wdfn-10l 3x3 package p d(max) = (125 c ? 25 c) / (49 c/w) = 2.04w for sop-8 (exposed pad) package the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curves in figure 6 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. sw boot 5v 0.1f rt7231/32/33/34 be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. external bootstrap diode connect a 0.1 f low esr ceramic capacitor between the boot and sw pins. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and the boot pin for efficiency improvement when input voltage is lower than 5.5v or duty ratio is higher than 65%. the bootstrap diode can be a low cost one such as 1n4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the rt7231/32/33/34. note that the external boot voltage must be lower than 5.5v
rt7231/32/33/34 15 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. layout consideration follow the pcb layout guidelines for optimal performance of the rt7231/32/33/34 ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` sw node is with high frequency voltage swing and should be kept at small area. keep sensitive components away from the sw node to prevent stray capacitive noise pickup. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the rt7231/32/33/34 fb pin. ` the gnd and exposed pad should be connected to a strong ground plane for heat sinking and noise protection. (a). for tssop-14 (exposed pad) package figure 6. derating curve of maximum power dissipation figure 7. pcb layout guide (c). for sop-8 (exposed) package en fb pvcc ss vin boot gnd sw gnd 2 3 4 5 6 7 8 9 c2 c1 c6 l1 v out c7 v out c4 c5 r1 r2 gnd input capacitor must be placed as close to the ic as possible. sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the resistor divider must be connected as close to the device as possible. 0.0 0.6 1.2 1.8 2.4 3.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb tssop-14 (exposed pad) wdfn-10l 3x3 sop-8 (exposed pad) (b). for wdfn-10l 3x3 package fb vin pgnd gnd ss pvcc pgood en pgnd sw sw boot vout vinr 4 2 3 5 7 6 11 13 12 10 8 9 14 pgnd 15 r2 r1 c vcc c in c boot l v out c out sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. place the feedback components as close to the fb as possible for better regulation. place the input and output capacitors as close to the ic as possible. v out pgnd c in l v out v out c vcc r2 r1 pgnd sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. en fb pgood ss vin vin boot sw sw pvcc 9 8 7 1 2 3 4 5 10 6 pgnd 11 c boot c out pgnd place the feedback components as close to the fb as possible for better regulation. place the input and output capacitors as close to the ic as possible.
rt7231/32/33/34 16 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 1.000 1.200 0.039 0.047 a1 0.000 0.150 0.000 0.006 a2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 d 4.900 5.100 0.193 0.201 e 0.650 0.026 e 6.300 6.500 0.248 0.256 e1 4.300 4.500 0.169 0.177 l 0.450 0.750 0.018 0.030 u 1.900 2.900 0.075 0.114 v 1.600 2.600 0.063 0.102 14-lead tssop (exposed pad) plastic package
rt7231/32/33/34 17 ds7231/32/33/34-00 march 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
rt7231/32/33/34 18 ds7231/32/33/34-00 march 2013 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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